27-inch 240Hz 1ms HDR1000 QD MiniLED MiniLED Liftable Gaming Monitor
$2,262.00
- Description
Description
| Model Number | ESHXM270GD243048-RF | ||||
|---|---|---|---|---|---|
| Brand Name | huaxin | ||||
| origin | China | ||||
| Small Orders | Accepted | ||||
Key Specifications/ Special Features:
27-inch 240Hz 1ms HDR1000 QD MiniLED MiniLED Liftable Gaming Monitor
| Part NO. | ESHXM270GD243048-RF |
| Panel size | 27 inch MiniLED monitor |
| resolution | 1920×1080 |
| Brightness | MAX 1200nit |
| interface | SPI |
| view angle | free view angle |
| Screen ratio | 16:09 |
| Refresh rate | 240HZ |
| Color gamut | 98% DCI-P3 |
| brightness | MAX 1200nit |
| contrast | 1000000:1 |
| Viewing angle | 178° |
| Response time | 1mS |
| Rated power | MAX 120W |
| size | 613 x 363 x 9.8mm |
| Trademark | Right Fortune |
| Specification | ROHS |
| Origin | Dong Guan China |
Appearance details：
Backboard outline dimension diagram：
Outline dimension diagram of BCON board：
Note: The maximum thickness of BCON board is 3mm
Power interface：
| Foot number | definition | description |
|---|---|---|
| 1-7 | GND | GND. |
| 8 | FB | VLED_ADJ |
| 9-15 | VLED | 26V MAX_7A |
SPI communication interface：
| Foot number | definition | description |
|---|---|---|
| 1 | SYS_PD_EN | Backlight power enable pin |
| 2 | SPI_MISO | SPI output signal |
| 3 | SPI_MOSI | SPI main output signal |
| 4 | SPI_SCK | SPI clock signal |
| 5 | SPI_CSB | SPI chip selection signal |
| 6 | SPI_VSYNC | SPI field synchronization signal |
| 7 | NC/GPIO | NC |
| 8-10 | GND | GND |
| 11-15 | NC | NC |
Communication Protocol
1 Physical Layer Protocol
1.1 The physical bus interface is an SPI interface.
1.2 SPI output clock frequency is 16MHz; SPI protocol, CS low level is the effective chip selection level; Idle Clock
The state is low, sampling data at the first transition edge (CPOL=0, CPHA=0); SPI is in 16 bit mode; High position ahead.
1.3 Use a set of SPI (SPI0) to output a complete frame of data, which is sent sequentially from left to right and top to bottom.
1.4 Provide Vsync field synchronization signal, with a default frame rate of 120HZ (Settings can be changed).
1.5 Physical frame format: Frame header (16 bit frame header: 0xAA55)+Application protocol field+16 bit CRC check field (16 bit CRC check,
Low byte first).
1.6 The 16 bit CRC check only covers the application protocol domain, and the check polynomial is: X ^ 16+X ^ 12+X ^ 5+1, with a mode of
CRC-CCCITT_LALSE mode, specific C language program implementation can be found in the notes.
2 Application Layer Protocol
Application protocol domain: The application protocol domain includes: command domain (two bytes)+command domain (two bytes)+application data domain.
2.1 Data frame: The application data domain of the data frame includes the brightness data of the 2304 partition of a frame of picture
2.2 The backlight panel partition is arranged in 24 rows and 48 columns, as shown in the sheet screen frame matrix format (ZONE_X_Y, where X is the row,
Y is the column), with a total of 1152 partitions. Each partition (ZONE_X_Y) corresponds to a 16 bit data (the top 6 bits are current values, and the bottom 10 bits are PWM values)
Value).
2.3 One frame of data corresponds to 1152 partitions, and the transmission order of frame data is from left to right and from top to bottom in the frame image matrix
send out.
Specs
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